1. Field of the Invention
The present invention relates to a system LSI chip having a test structure (test element group: hereinafter abbreviated as TEG) for wires.
2. Description of the Background Art
In a semiconductor device such as an LSI, fining down and layer multiplication of wires progress following fining down and high integration of elements. A wire structure including an interlayer isolation film and a process of manufacturing the same are complicated due to such fining down and layer multiplication of the wires, and it is not too much to say that workmanship of the wires influences the performance and the yield of a product. The workmanship of the wires must be correctly and quickly evaluated for improvement of the yield and process control. Workmanship evaluation of the wires includes various types. For example, there is an evaluation immediately after manufacturing steps for checking whether or not abnormality such as disconnection or shorting is caused by a random factor such as a failure or contamination, whether or not the wires have been formed in a designed width and the like. Another example of evaluation is reliability assessment with an acceleration test for checking aging (occurrence of voids in the wires caused by migration etc.) of a completed chip.
While the workmanship of the wires in the product chip themselves must be evaluated independently of the remaining circuit elements included in the product chip, it is difficult and inefficient to perform such evaluation employing the product chip.
Therefore, the evaluation is generally made employing various TEGs formed with only wire structures. More specifically, the wires are evaluated by measuring a parameter such as the resistance value of such a wire TEG and detecting a portion having deficiency or abnormality by an optical method such as observation with an emission microscope or OBIC (optical beam induced current) analysis when the parameter is different from a designed value.
In general, a test wafer formed with only a wire TEG is manufactured independently of a product wafer, or a wire TEG region is provided on a region of a product wafer excluding a product chip region.
In the former case, however, the test wafer manufactured independently of the product wafer may not correctly reflect abnormality caused in the product wafer by a random factor. Statistical investigation is necessary for improving the detection rate of abnormality caused by a random factor. Consequently, the test wafer must be prepared frequently. However, the cost for the product is disadvantageously increased in this case.
In the latter case, the area occupied by the product chip is reduced due to the wire TEG region provided in the product wafer. Consequently, the yield of the product chip is reduced, to result in increase of the cost for the product. While the area of the wire TEG region may be reduced for avoiding increase of the cost, the detection rate for abnormality caused by a random factor is reduced if the area of the wire TEG region is reduced. Thus, sufficient investigation on the product cannot be expected in this case.
Thus, in the conventional mode of wire TEGs, the cost is inevitably increased in order to improve the detection rate for abnormality caused by a random factor in the product chip.
To this end, it is conceivable to build wire TEGs into the product chip itself. In other words, some free spaces present in the product chip may be utilized as wire TEG forming regions. Japanese Patent Application Laid-Open No. 5-144917 (1993) describes an example of such a technique. FIG. 9 is a plan view showing a chip CP2 for illustrating this technique. The chip CP2 includes free spaces 301 formed with substrate wire TEGs, a region 302 formed with internal cells and normal wires and regions 303 formed with I/O cells.
According to this technique forming the wire TEGs in the product chip, abnormality caused in the product chip by a random factor can be detected without manufacturing a number of test wafers. Further, the free spaces in the product chip are utilized, not to reduce the yield of the product chip. Thus, the workmanship of the wires can be evaluated while avoiding the problems arising in the conventional wire TEGs.
However, Japanese Patent Application Laid-Open No. 5-144917 disclosing this technique describes only that the wire TEGs are formed on the free spaces (four corners of the chip, for example) in the product chip with no consideration on variation of effects with positions for forming the wire TEGs. In the case of the chip CP2 shown in FIG. 9, the wire TEGs are formed in the regions different from the region 302 formed with the internal cells and normal wires and the I/O cell forming regions 303 in plan view. When thus avoiding the regions functioning as the product (hereinafter referred to as product regions) in plan view, however, there is such a possibility that only extremely small free spaces are left and the wire TEG regions cannot have sufficient areas.
A chip having a multilayer wire structure may have a wide free space in addition to a plane provided with a product region. In a system LSI chip integrating a memory part and a logic part, the logic part requires a multilayer wire structure having wires present over a number of layers, while about two upper wire layers necessary for power supply/ground wires may be present in the memory part in general. Therefore, a considerably wide free space, corresponding to the area of the memory part, is present on the upper wire layers of the memory part.
In the system LSI, however, metal films, referred to as dummy patterns, of about several xcexcm square are generally spread over this free space. The dummy patterns are provided in order not to cause dishing (dish-shaped depressions) on the surface of an interlayer isolation film of the memory part when performing chemical mechanical polishing (hereinafter abbreviated as CMP) for forming wire films of the multi-layer wire structure of the logic part and to attain roughness balance of the metal films for preventing occurrence of etching rate difference between the logic part and the memory part due to small areas of the metal films in the memory part when forming patterns of the wire films of the logic part.
FIGS. 10 to 12 illustrate the structure of such a system LSI chip CP1. FIG. 10 is a plane layout diagram of a memory part MM and a logic part LG on the chip CP1, and FIG. 11 is a plan view showing a region RG on the memory part MM in an enlarged manner for illustrating the arrangement of dummy patterns DP formed in a free space on a memory array. Referring to FIG. 10, the memory part MM is designed in a scale substantially identical to that of the logic part LG. While such memory parts MM occupy system LSI chips in various area rates, the memory part MM generally occupies a somewhat large part in the total area of the system LSI chip CP1.
FIG. 12 is a sectional view taken along the line Cxe2x80x94C in FIG. 11. As shown in FIG. 12, the memory part MM comprises an element layer 402 having a number of memory cells MC (sets of DRAMs and capacitors, for example) on a substrate 401, while a wire layer 403 having power supply/ground wires IL1 and IL2 and a dummy pattern layer 404 formed with a number of dummy patterns DP are provided thereon. The dummy patterns DP have surfaces flush with the surfaces of wires (not shown) of respective layers in a multilayer wire structure of the logic part LG. Referring to FIG. 12, the dummy pattern layer 404 includes three layers, for example. Interlayer isolation films IS0, IS1, IS2, IS3 and IS4 are formed between the memory cells MC and the power supply/ground wires IL1, between the power supply/ground wires IL1 and the power supply/ground wires IL2, between the power supply/ground wires IL2 and the dummy pattern layer 404 and between the respective layers of the dummy pattern layer 404 respectively for isolating these layers from each other. A passivation film PV protecting the surfaces is formed on the uppermost dummy patterns DP. FIG. 12 illustrates the layer formed with the wires IL1, located immediately on the element layer 402, as a first layer, the layer formed with the wires IL2 as a second layer, and the respective layers of the dummy pattern layer 404 as third, fourth and fifth layers in ascending order respectively.
Thus, the third to fifth layers of the memory part MM of the chip CP1, having allowance for forming a wire region in an extent substantially identical to the area of the memory part MM, are only employed as dummy patterns.
According to a first aspect of the present invention, a system LSI chip comprises a substrate having first and second regions on its surface, a multilayer wire structure formed on the first region of the substrate, an element layer, formed on the second region of the substrate, having a memory cell, an interlayer isolation film formed on the element layer, and a wire test structure formed on the interlayer isolation film over the whole area of the second region.
In the system LSI chip according to the first aspect of the present invention, the wire test structure is formed on the interlayer isolation film located on the second region, whereby abnormality caused in the system LSI chip by a random factor such as a failure or contamination can be detected and workmanship of the wire test structure can be evaluated independently of the remaining elements in the system LSI chip. Further, the wire test structure can be formed in a large scale over the whole area of the second region on the element layer through the interlayer isolation film, whereby the detection rate for abnormality caused in the system LSI chip by a random factor such as a failure or contamination is increased as compared with the case of forming the wire test structure on a small free space in the same plane as the second region. After evaluation of the workmanship, the wire test structure functions also as an electric shielding structure for the second region.
According to a second aspect of the present invention, the wire test structure is a series of wire structures having a number of via hole connection parts.
According to a third aspect of the present invention, the wire test structure has interdigital electrodes.
According to a fourth aspect of the present invention, the wire test structure comprises a single wire presenting a zigzag pattern.
According to a fifth aspect of the present invention, the multilayer wire structure and the wire test structure are formed through a common step.
In the system LSI chip according to the fifth aspect of the present invention, the wire test structure is formed through the step in common with the multilayer wire structure, whereby the wire test structure located on the second region is also subjected to CMP when forming the multilayer wire structure located on the first region by CMP so that dishing is hardly caused on the surface of the interlayer isolation film located on the second region while roughness balance of wire films can be ensured between the first region and the second region. In other words, the wire test structure functions also as a dummy pattern.
According to a sixth aspect of the present invention, a fixed potential is supplied to part of the wire test structure.
In the system LSI chip according to the sixth aspect, a single electrode pad can be omitted as to a single wire TEG pattern, whereby the number of electrode pads requiring a wide area can be reduced and electrode pads for a product region can be widely provided. Further, the wire test structure supplied with the fixed potential becomes a conductor film whose potential is fixed after completion of workmanship evaluation, to attain a more effective electric shielding function.
According to a seventh aspect of the present invention, the system LSI chip according to the fifth aspect further comprises an electrode pad, connected with the wire test structure, having a surface flush with a part of the wire test structure furthest from the substrate.
In the system LSI chip according to the seventh aspect, a portion of deficiency or abnormality can be detected with an optical method in a state having no upper wire layer serving as a screen for the wire test structure, whereby the abnormality can be readily detected.
According to an eighth aspect of the present invention, a method of manufacturing a system LSI chip comprises steps (a) to (e) of (a) preparing a substrate having first and second regions on its surface, (b) forming an element layer having memory cells on the second region, (c) forming a first interlayer isolation film on the first region and on the element layer, (d) forming a first conductor film on the first interlayer isolation film, and (e) patterning the first conductor film for forming a multilayer wire structure on the first interlayer isolation film located on the first region while forming a wire test structure extending over the whole area of the second region on the first interlayer isolation film located on the second region.
According to a ninth aspect of the present invention, the wire test structure is a series of wire test structures having a number of via hole connection parts.
According to a tenth aspect of the present invention, the wire test structure has interdigital electrodes.
According to an eleventh aspect of the present invention, the wire test structure comprises a single wire presenting a zigzag pattern.
According to a twelfth aspect of the present invention, the method of manufacturing a system LSI chip according to the eighth aspect further comprises, when forming the wire test structure and the multilayer wire structure to extend also along the thickness of the substrate, steps (f) to (i) of (f) further forming a second interlayer isolation film to cover the wire test structure and the multilayer wire structure, (g) patterning the second interlayer isolation film for forming a via hole exposing the wire test structure and the multilayer wire structure, (h) forming a second conductor film on the second interlayer isolation film subsequently to the step (g), and (i) patterning the second conductor film for forming the multilayer wire structure to extend above the second interlayer isolation film located on the first region and forming the wire test structure to extend above the second interlayer isolation film located on the second region.
According to a thirteenth aspect of the present invention, the wire test structure is a series of wire structures having a number of via hole connection parts.
According to a fourteenth aspect of the present invention, the wire test structure has interdigital electrodes.
According to a fifteenth aspect of the present invention, the wire test structure comprises a single wire presenting a zigzag pattern.
According to a sixteenth aspect of the present invention, the method of manufacturing a system LSI chip according to the twelfth aspect also forms an electrode pad connected to the wire test structure above the first or second interlayer isolation film when the step (e) or step (i) is a step of forming a part of the wire test structure furthest from the substrate.
In the method of manufacturing a system LSI chip according to the sixteenth aspect, the electrode pad connected to the wire test structure is also formed when forming the part of the wire test structure furthest from the substrate, whereby workmanship of the wire test structure can be evaluated immediately after forming the wire test structure for detecting abnormality and selecting a defective chip in an early stage of the process. Thus, it is possible to not perform a subsequent process on the defective chip having abnormality in its wire, in order to avoid waste. Further, a portion of deficiency or abnormality can be detected with an optical method in a state having no upper wire layer serving as a screen for the wire test structure, whereby the abnormality can be readily detected.
According to a seventeenth aspect of the present invention, the wire test structure is a series of wire structures having a number of via hole connection parts.
According to an eighteenth aspect of the present invention, the wire test structure has interdigital electrodes.
According to a nineteenth aspect of the present invention, the wire test structure comprises a single wire presenting a zigzag pattern.
An object of the present invention is to utilize a dummy pattern layer in a free space on memory cells of a memory part of a system LSI chip, which has not been effectively used, as a large-scale wire TEG region while leaving a dummy pattern function.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.